Mô-đun DDR 32-bit tùy chỉnh XQVR300, được xử lý chống bức xạ, ứng dụng hàng không vũ trụ, thay thế 1:1, hiệu năng cao, giá thành cao, sẵn sàng đặt hàng
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Mô-đun DDR 32-bit tùy chỉnh XQVR300, được xử lý chống bức xạ, ứng dụng hàng không vũ trụ, thay thế 1:1, hiệu năng cao, giá thành cao, sẵn sàng đặt hàng

5
827
Đã bán
2.676.095đ
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Mô-đun DDR 32-bit tùy chỉnh XQVR300, được xử lý chống bức xạ, ứng dụng hàng không vũ trụ, thay thế 1:1, hiệu năng cao, giá thành cao, sẵn sàng đặt hàng
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Specification
XQVR300-4CB228B FPGAs Overview
The QPro Virtex XQVR300-4CB228B delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in
silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive
5-layer-metal 0.22 µm CMOS process. These advances make QPro Virtex XQVR300-4CB228B FPGAs powerful and flexible alternatives to
mask-programmed gate arrays.
Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in
programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible
interconnect resources, and advanced process technology, the QPro VirtexXQVR300-4CB228B delivers a high-speed and high-capacity
programmable logic solution that enhances design flexibility while reducing time-to-market.

Product Description
Features
• 0.22 µm 5-layer epitaxial process
• QML certified
• Radiation-hardened FPGAs for space and satellite applications
• Guaranteed total ionizing dose to 100K Rad(si)
• Latch-up immune to LET = 125 MeV cm2/mg
• SEU immunity achievable with recommended redundancy implementation
• Guaranteed over the full military temperature range (–55°C to +125°C)
• Fast, high-density Field-Programmable Gate Arrays
• Densities from 100k to 1M system gates
• System performance up to 200 MHz
• Flexible architecture that balances speed and density
• Dedicated carry logic for high-speed arithmetic
• Dedicated multiplier support
• Cascade chain for wide-input functions
• Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset
• Internal 3-state bussing
• IEEE 1149.1 boundary-scan logic
• Die-temperature sensing device
• Supported by FPGA Foundation and Alliance Development Systems
• Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager
• Wide selection of PC and workstation platforms
• SRAM-based in-system configuration
• Unlimited reprogrammability
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